View SI9910_296758.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SI9910
Vishay Siliconix
Industrial and Office Automation SI9910
Adaptive Power MOSFET Drivera
FEATURES
* dv/dt and di/dt Control * Undervoltage Protection * Short-Circuit Protection * * * trr Shoot-Through Current Limiting Low Quiescent Current CMOS Compatible Inputs * Compatible with Wide Range of MOSFET Devices * Bootstrap and Charge Pump Compatible (High-Side Drive)
DESCRIPTION
The SI9910 Power MOSFET driver provides optimized gate drive signals, protection circuitry and logic level interface. Very low quiescent current is provided by a CMOS buffer and a high-current emitter-follower output stage. This efficiency allows operation in high-voltage bridge applications with "bootstrap" or "charge-pump" floating power supply techniques. The non-inverting output configuration minimizes current drain for an n-channel "on" state. The logic input is internally diode clamped to allow simple pull-down in high-side drives. Fault protection circuitry senses an undervoltage or output short-circuit condition and disables the power MOSFET. Addition of one external resistor limits maximum di/dt of the external Power MOSFET. A fast feedback circuit may be used to limit shoot-through current during trr (diode reverse recovery time) in a bridge configuration. The SI9910 is available in 8-pin plastic DIP and SOIC packages, and are specified over the industrial, D suffix (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
a. Patent Number 484116.
Applications information may also be obtained via FaxBack, request document #70579.
FaxBack 408-970-5600, request 70009 www.siliconix.com
S-60752--Rev. F, 05-Apr-99 1
SI9910
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VSS Pin VDD Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to 18 V Pin 1, 4, 5, 7, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 V to VDD + 0.3 V Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current (Ipk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 8-Pin SOIC (Y Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW 8-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 5.6 mW/C above 25C.
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Input
High Level Input Voltage Low Level Input Voltage Input Voltage Hysteresis High Level Input Current Low Level Input Current VIH VIL Vh IIH IIL VIN = VDD VIN = 0 V 0.90 0.70 x VDD 7.4 6.0 2.0 0.35 x VDD 3.0 1 1 A V
Limits
Symbol
VDD 10.8 V to 16.5 V TA = OperatingTemperature Range
Minc
Typb
Maxc
Unit
Output
High Level Output Voltage Low Level Output Voltage Undervoltage Lockout ISENSE Pin Threshold Voltage Drain-Source Maximum Input Current for VDS Input Peak Output Source Current Peak Output Sink Current VOH VOL VUVLO VTH VDS IVDS IOS+ IOSMax IS = 2 mA, Input High 100 mV Change on Drain Input High IOH = -200 mA IOL = 200 mA 8.3 0.5 8.3 VDD - 3 10.7 1.3 9.2 0.66 9.1 12 1 -1 3 10.6 V 0.8 10.2 20.0 A A
Supply
Supply Range Supply Current VDD IDD1 IDD2 Output High, No Load Output Low, No Load 10.8 0.1 100 16.5 1 500 V A
Dynamic
Propagation Delay Time Low to High Level Propagation Delay Time High to Low Level Rise Time Fall Time Overcurrent Sense Delay (VDS) Input Capacitance Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. tPLH tPHL tr tf tDS Cin CL = 2000 pF 120 135 50 35 1 5 S pF ns
S-60752--Rev. F, 05-Apr-99 2
FaxBack 408-970-5600, request 70009 www.siliconix.com
SI9910
Vishay Siliconix
AC TESTING CONDITIONS
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin 1: VDS Pin 1 or VDS is a sense input for the maximum source-drain voltage limit. Two microseconds after a high transition on input pin 2, an internal timer enables the VDS(max) sense circuitry. A catastrophic overcurrent condition, excessive on-resistance, or insufficient gate-drive voltage can be sensed by limiting the maximum voltage drop across the power MOSFET. An external resistor (R3) is required to protect pin 1 from overvoltage during the MOSFET "off" condition. Exceeding VDS(max) latches the SI9910 "off." Drive is re-enabled on the next positive- going input on pin 2. If pin 1 is not used, it must be connected to pin 6 (VSS). Pin 2: INPUT A non-inverting, Schmidt trigger input controls the state of the MOSFET gate-drive outputs and enables the protection logic. When the input is low ( VIL), VDD is monitored for an undervoltage condition (insufficiently charged bootstrap capacitor). If an undervoltage ( VDD(min)) condition exists, the driver will ignore a turn-on input signal. An undervoltage ( VDD(min)) condition during an "on" state will not be sensed. Pin 3: VDD VDD supplies power for the driver's internal circuitry and charging current for the power MOSFET's gate capacitance. The SI9910 minimizes the internal IDD in the "on" state (gatedrive outputs high) allowing a "floating" power supply to be provided by charge pump or bootstrap techniques.
FaxBack 408-970-5600, request 70009 www.siliconix.com
Pin 4: DRAIN Drain is an analog input to the internal dv/dt limiting circuitry. An external capacitor (C1) must be used to protect the input from exposure to the high-voltage ("off" state) drain and to set the power MOSFET's maximum rate of dv/dt. If dv/dt feedback is not used, pin 4 must be left open. Pin 5: ISENSE ISENSE in combination with an external resistor (R1) protects the power MOSFET from potentially catastrophic peak currents. ISENSE is an analog feedback that limits current during the power MOSFET's transition to an "on" state. It is intended to protect power MOSFETs (in a halfbridge arrangement) from "shoot-through" current, resulting from excess di/dt and trr of flyback diodes or from logic timing overlap. An 0.8-V drop across (R1) should indicate a current level that is approximately four times the maximum allowable load current. When the ISENSE input is not used, it should be tied to pin 6 (VSS). Pin 6: VSS VSS is the driver's ground return pin. The applications diagram illustrates the connection of VSS for sourcereferenced "floating" applications (half-bridge, high-side) and ground-referenced applications (half-bridge, low-side).
S-60752--Rev. F, 05-Apr-99 3
SI9910
Vishay Siliconix
Pin 7: PULL-DOWN Pin 8: PULL-UP Pull-up and pull-down outputs collectively provide the power MOSFET gate with charging and discharging currents. Turn "on" or "off" di/dt can be limited by adding resistance (R2) in series with the appropriate output. particular limitations, or both techniques if switching losses must be minimized and static operation is necessary. The schematic above illustrates both the charge pump and bootstrap circuits used in conjunction with an SI9910 in a high-side driver application. Input signal level shifting is accomplished with a passive pullup (R4) and n-channel MOSFET (Q2) for pull-down in applications below 500 V. Total node capacitance defines the value of R4 needed to guarantee an input transition rate which safely exceeds the maximum dv/dt rate of the output halfbridge. Using level-shift devices with higher current capabilities may necessitate the addition of current-limiting components such as R5. Bootstrap Undervoltage Lockout When using a bootstrap capacitor as a high-side floating supply, care must be taken to ensure time is available to recharge the bootstrap capacitor prior to turn-on of the highside MOSFET. As a catastrophic protection against abnormal conditions such as start-up, loss of power, etc., an internal voltage monitor has been included which monitors the bootstrap voltage when the SI9910 is in the low state. The SI9910 will not respond to a high input signal until the voltage on the bootstrap capacitor is sufficient to fully enhance the power MOSFET gate. For more details, please refer to Application Note AN705, which may be obtained via FaxBack, request document #70579.
APPLICATIONS
"Floating" High-Side Drive Applications As demonstrated in Figure 1, the SI9910 is intended for use as both a ground-referenced gate driver and as a "high-side" or source-referenced gate driver in half-bridge applications. Several features of the SI9910 permit its use in half-bridge high-side drive applications. A simple and inexpensive method of isolating a floating supply to power the SI9910 in high-side driver applications had to be provided. Therefore, the SI9910 was designed to be compatible with two of the most commonly used floating supply techniques: the bootstrap and the charge pump. Both of these techniques have limitations when used alone. A properly designed bootstrap circuit can provide lowimpedance drive which minimizes transition losses and the charge pump circuit provides static operation. The SI9910 is configured to take advantage of either floating supply technique if the application is not sensitive to their
S-60752--Rev. F, 05-Apr-99 4
FaxBack 408-970-5600, request 70009 www.siliconix.com
SI9910
Vishay Siliconix
FIGURE 1. High-Voltage Half-Bridge with SI9910 Drivers
FaxBack 408-970-5600, request 70009 www.siliconix.com
S-60752--Rev. F, 05-Apr-99 5

▲Up To Search▲

Price & Availability of SI9910

	To Download SI9910 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .